IBM Architectural

The System/360 series had a computer system architecture specification. This specification does not make any assumptions on the implementation itself, but rather describes the interfaces and the expected behavior of an implementation. The architecture describes mandatory interfaces that must be available on all implementations and optional interfaces which may or may not be implemented.

Some of the aspects of this architecture are:

  • Big endian byte ordering
  • A processor with
    • 16 32-bit General purpose registers (R0-R15)
    • A 64-bit Program status word (PSW) which describes (among other things)
    • An interruption mechanism, maskable and unmaskable interruption classes and subclasses
    • An instruction set. Each instruction is wholly described and also defines the conditions under which an exception is recognized in the form of program interruption.
  • A memory (called storage) subsystem with
    • 8 bits per byte
    • A special processor communication area starting at address 0
    • 24-bit addressing
  • Manual control operations that allow
    • A bootstrap process (a process called Initial Program Load or IPL)
    • Operator-initiated interrupts
    • Resetting the system
    • Basic debugging facilities
    • Manual display and modifications of the system's state (memory and processor)
  • An Input/Output mechanism - which does not describe the devices themselves

Some of the optional features are:

All models of System/360, except for the Model 20, implemented that specification.

Binary arithmetic and logical operations could be performed as register-to-register and as memory-to-register/register-to-memory as a standard feature. If the Commercial Instruction Set option was installed, packed decimal arithmetic could be performed as memory-to-memory with some memory-to-register operations. The Scientific Instruction Set feature, if installed, provided access to fourfloating point registers that could be programmed for either 32-bit or 64-bit floating point operations. The Models 85 and 195 could also operate on 128-bit extended-precision floating point numbers stored in pairs of floating point registers, and software provided emulation in other models. The System/360 used an 8-bit byte, 32-bit word, 64-bit double-word, and 4-bit nibble. Machine instructions had operators with operands, which could contain register numbers or memory addresses. This complex combination of instruction options resulted in a variety of instruction lengths and formats.

Memory addressing was accomplished using a base-plus-displacement scheme, with registers 1 through F (15). A displacement was encoded in 12 bits, thus allowing a 4096-byte displacement (0-4095), as the offset from the address put in a base register. Register 0 could not be used as a base register, as "0" was reserved to indicate an address in the first 4 KB of memory. This permitted initial execution of the IPL ("Initial Program Load" or boot) since base registers would not necessarily be set to 0 during the first few instruction cycles.

With the exception of the Model 67, all addresses were real memory addresses. Virtual memory was not available in most IBM mainframes until the System/370 series. The Model 67 introduced a virtual memory architecture which was used by MTS, CP-67, and TSS/360, but not by IBM's mainline System/360 operating systems.

The System/360 machine-code instructions were 2 (no memory operands), 4 (one operand), or 6 bytes (two operands) long. Instructions were always situated on 2-byte boundaries.

Operations like the MVC (Move-Character) (Hex: D2) could only move at most 256 bytes of information. Moving more than 256 bytes of data required multiple MVC operations. (The System/370 series introduced a family of more powerful instructions such as the MVCL "Move-Character-Long" instruction, which allows 16 MB to be moved at once.)

An operand was two bytes long, typically representing an address as a 4-bit nibble denoting a base register and a 12-bit displacement relative to the contents of that register, in the range 000–FFF(shown here as hexadecimal numbers). The address corresponding to that operand would be the contents of the specified general-purpose register plus the displacement. For example, an MVC instruction that moved 256 bytes (with length code 255 in hexadecimal as FF) from base register 7, plus displacement 000, to base register 8, plus displacement 001, would be coded as the 6-byte instruction "D2FF 8001 7000" (operator/length/address1/address2).

The System/360 was designed to separate the "system state" from the "problem state". This provided a basic level of security and recoverability from programming errors. Problem (user) programs could not modify data or program storage associated with the system state. Addressing, data, or operation exception errors caused the system state to be entered through a controlled routine allowing the operating system to attempt to correct or terminate the program in error. Similarly, certain processor hardware errors could be recovered through the "machine check" routines.


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